Примери коришћења Memory hierarchy на Енглеском и њихови преводи на Српски
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This is a general memory hierarchy structuring.
CMOx memory technology stretches the Flash space in the memory hierarchy[3].
The lower levels of the memory hierarchy tend to be slower, but larger.
Adding complexity slows down the memory hierarchy.
The location in the memory hierarchy dictates the time required for the prefetch to occur.[5].
Neither of them is uniform, butis specific to a particular component of the memory hierarchy.
The number of levels in the memory hierarchy and the performance at each level has increased over time.
Spatial locality is improved because elements with consecutive memory addresses tend to be pulled up the memory hierarchy together.
McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive.
Hierarchical memory is a hardware optimization that takes the benefits of spatial and temporal locality andcan be used on several levels of the memory hierarchy.
Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data.
For example, the memory hierarchy of an Intel Haswell Mobile processor circa 2013 is: Processor registers- the fastest possible access(usually 1 CPU cycle).
Additionally, for large data sets,the near-random memory access patterns of many integer sorting algorithms can handicap them compared to comparison sorting algorithms that have been designed with the memory hierarchy in mind.
Processor registers are at the top of the memory hierarchy, and provide the fastest way for a CPU to access data.
Memory hierarchy affects performance in computer architectural design, algorithm predictions, and lower level programming constructs involving locality of reference.
In memory subsystems that use caches, the word-sized transfer is the one between the processor and the first level of cache;at lower levels of the memory hierarchy larger transfers(which are a multiple of the word size) are normally used.
At lower levels of the memory hierarchy larger transfers(which are a multiple of the word size) are normally used.
A common optimization is to put the unsorted elements of the buckets back in the original array first, then run insertion sort over the complete array; because insertion sort's runtime is based on how far each element is from its final position,the number of comparisons remains relatively small, and the memory hierarchy is better exploited by storing the list contiguously in memory. .
Load responses from a memory hierarchy which includes CPU caches and DRAM do not have a deterministic delay.
The term memory hierarchy is used in computer architecture when discussing performance issues in computer architectural design, algorithm predictions, and the lower level programming constructs such as involving locality of reference.
Virtual memory makes application programming easier by hiding fragmentation of physical memory; by delegating to the kernel the burden of managing the memory hierarchy(eliminating the need for the program to handle overlays explicitly); and, when each process is run in its own dedicated address space, by obviating the need to relocate program code or to access memory with relative addressing.
Interaction with memory hierarchy effects can make this overhead intolerable in circumstances that are hard to predict or to detect in routine testing.
CMOx memory technology stretches the Flash space in the memory hierarchy One of the main ways to increase system performance is minimising how far down the memory hierarchy one has to go to manipulate data.
Predicting where in the memory hierarchy the data resides is difficult… the location in the memory hierarchy dictates the time required for the prefetch to occur.
Taking optimal advantage of the memory hierarchy requires the cooperation of programmers, hardware, and compilers(as well as underlying support from the operating system).
The overall goal of using a memory hierarchy is to obtain the highest possible average access performance while minimizing the total cost of the entire memory system(generally, the memory hierarchy follows the access time with the fast CPU registers at the top and the slow hard drive at the bottom).
Finally, at the other end of the memory hierarchy, the CPU register file itself can be considered the smallest, fastest cache in the system, with the special characteristic that it is scheduled in software-typically by a compiler, as it allocates registers to hold values retrieved from main memory, .
Taking optimal advantage of the memory hierarchy requires the cooperation of programmers, hardware, and compilers(as well as underlying support from the operating system): Programmers are responsible for moving data between disk and memory through file I/O. Hardware is responsible for moving data between memory and caches.