What is the translation of " 时钟周期 " in English?

• clock cycle
• clock cycles
• clock period

Examples of using 时钟周期 in Chinese and their translations into English

下降沿），这将出现每256个PCA时钟周期。
(falling edge), which will occur every 256 PCA clock cycles.

在每个SPI时钟周期内，都会发生全双工数据传输。
During each SPI clock cycle, a full-duplex data transmission occurs.

从中断处理程序返回需要4个时钟周期。
A return from an interrupt handling routine takes four clock cycles.

端口1的引脚每个时钟周期都在采样。
The pins of Port 1 are sampled every clock cycle.

在待机模式下，器件唤醒在6个时钟周期。
From Standby mode, the device wakes up in six clock cycles.

只是在每个时钟周期中发送了更多的指令。
They simply send more instructions in every clock cycle.

他们只是在每个时钟周期中发送了更多的指令。
They simply send more instructions in every clock cycle.

只基于时钟周期定时。
Solely on clock cycle timing.

但是，这意味着每个传输需要两个时钟周期。
What this means is that two transfers occur every clock cycle.

的基本总线周期由4个时钟周期组成。
Thus length of bus cycle in 8086 is four clock cycle.

你可以阅读一个C程序，“看到”每个时钟周期。
You can read a C program and"see" every clock cycle.

端口1的管脚每个时钟周期采.
The pins of Port 1 are sampled every clock cycle.

这个概念实现了每个时钟周期执行的指令。
This concept enables instructions to be executed in every clock cycle.

内部数据流水线操作，列地址可在每个时钟周期里改变.
Internal pipelined operation; column address can be changed every clock cycle.

内部指令时钟周期.
Internal instruction cycle clock.

每条指令需要花费若干时钟周期.
Each instruction takes a number of clock cycles.

数据转移到主存中处理花费300个时钟周期，此时CPU没有做任何事情。
It costs 300 clock cycles to go out to main memory, at which time the CPU isn't doing anything.

所以，虽然需要花费5个时钟周期来执行每条指令，但是可以同时执行5条指令的各个阶段。
So even though it might take five clock cycles to execute each instruction, there can be five instructions in various stages of execution simultaneously.

时钟周期就是时钟循环重复一次的时间间隔，通常用ns度量。
The clock period is the time interval to repeat one clock cycle, usually measured in nanoseconds(nsec).

如果不知道时钟周期的时间，就不可能了解一组数字是否比另一组数字更快。
Without knowing the clock cycle times, it is impossible to state if one set of numbers is"faster" than another.

例如，标准SPI模式下需花费40个时钟周期才能完成的任务现在可以在40/4=10个时钟周期内完成。
So for example, a task that takes 40 clock cycles to complete in standard SPI mode can now be completed in 40/4= 10 clock cycles.

在这种情况下，通过同步器的延迟时间tpd为一个系统时钟周期。
In this case, the delay tpd through the synchronizer is one system clock period.

假设该芯片有一个15步的工作流程，每个时钟周期可以发送4条指令。
Assume it has a 15-stage pipeline and can issue four instructions every clock cycle.

如果需要等待一段时间（例如进行模数转换），主器件在发出时钟周期之前必须至少等待这段时间。
If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.

在该图中，每个接收(Rx)和发送(Tx)间隔之间的时间是在系统时钟周期中测量的。
In the figure, the time between each receive(Rx) and transmit(Tx) interval is measured in system clock cycles.

在这种架构中，一个CPU交替处理指令的读取、解码和执行，每个时钟周期处理一条指令。
In this architecture, a single CPU overlaps fetching, decoding and executing instructions to process one instruction each clock cycle.

在AT89LP216中，指令可能需要1，2，3甚至4个时钟周期完成。
Instructions in the AT89LP213/214 may take 1, 2, 3 or 4 clock cycles to complete.

举例来说，DDR3-2000内存的时钟频率是1000MHz，其时钟周期为1ns。
For example, DDR3-2000 memory has a 1000 MHz clock frequency, which yields a 1 ns clock cycle.

假设它有一个15-stage的pipeline，每个时钟周期可以发出四条指令。
Assume it has a 15-stage pipeline and can issue four instructions every clock cycle.

芯片本身具有740kHz时钟，每条指令使用8个时钟周期。
The chip itself had 740 kHz clock, using 8 clock cycles per instruction.