时钟 信号 英语是什么意思 - 英语翻译

• clock signal
• clock signals

在 中文 中使用 时钟 信号 的示例及其翻译为 英语

检测时钟信号是否短路到其他线路。
Testing the clock signal whether short circuit to the other lines.

检测时钟信号是否短路到其他线路。
Tests whether the clock signal short circuit to the other lines.

该值越小越容易生成稳定的时钟信号。
A smaller ESR indicates easier generation of stable clock signals.

检测时钟信号是否短路到其它线路。
Testing the clock signal whether short circuit to the other lines.

地址、数据输入和其它控制信号均与时钟信号相关.
Address, data in and other control signals are associated with the clock signals.

检测时钟信号是否短路到其它线路。
Tests whether the clock signal short circuit to the other lines.

Manchester编码和其他方案通过增加时钟信号解决了这些问题。
Manchester coding and other solutions solve these problems by increasing the clock signal.

时钟信号和复位信号.
A clock signal and a data signal..

锁存信号也须要与时钟信号协调才能显示出完整的图象。
The latch signal also needs to be coordinated with the clock signal in order to display a complete image.

RBNC系统产生CCD读取时钟信号，并包括处理有效载荷数据的输出处理单元和编码系统。
The RBNC system generates CCD reading clock signals, and includes output processing units and encoding systems that handle the payload data.

锁存信号也须与时钟信号协调才能显示出完整的图象。
The latched signal also needs to be coordinated with the clock signal to display the complete image.

主机向每种卡的5号接点提供时钟信号，但各种卡的时钟频率可能不同。
A clock signal is provided by the host to contact no. 5 of each card but the clock rate may be different.

由于UART中没有时钟信号，因此两个器件在传输开始之前必须配置波特率。
Since there are no clock signals in UART, both devices must be configured with a baud rate before transmission begins.

Dante技术可以在以太网(100M或者1000M)上传送高精度时钟信号以及专业音频信号并可以进行复杂的路由。
Dante technology delivers high-precision clock signals as well as professional audio signals over Ethernet(100M or 1000M) and enables complex routing.

锁存信号也需要与时钟信号协调，以便显示完整的图像。
The latch signal also needs to be coordinated with the clock signal in order to display a complete image.

时钟信号也可能由门控，即用一个控制信号使能或关闭电路某一部分的时钟信号。
A clock signal might also be gated, that is, combined with a controlling signal that enables or disables the clock signal for a certain part of a circuit.

通常，我们知道，在微处理器和微控制器的设计中，OSC晶振用于提供时钟信号。
In general, we know that, crystal oscillators are used in the microprocessors and microcontrollers for providing the clock signals.

该公司采用“4相时钟”方案，使时钟信号加倍，以提高数据传输速度和稳定性。
The Company adopted a'4-Phase Clocking' scheme, which doubles the clock signal to boost data transfer speed and stability.

任何同步系统都有一个控制时钟信号，它同步系统中的所有模块，使它们同时发生变化。
Any synchronous system has one controlling clock signal that synchronizes all of the blocks in the system making them change at the same time.

该公司采用“4相时钟”方案，使时钟信号加倍，以提高数据传输时延和稳定性。
The Company adopted a'4-Phase Clocking' scheme, which doubles the clock signal to boost data transfer speed and stability.

应该提到的是，时钟信号是周期性的高低信号，它控制着这个同步系统的定时。
It should be mentioned that the clock signal is the periodic high-low signal that controls the timing to this synchronous system.

AESx数据流内嵌了时钟信号，所以简单的系统无需额外连接专用的字时钟。
AESx has the clock signal embedded in the data stream, so a dedicate word clock connection is often not needed for simple systems.

该公司采用“4相时钟”方案，使时钟信号加倍，以提高数据传输速率单位单位和稳定性。
The Company adopted a'4-Phase Clocking' scheme, which doubles the clock signal to boost data transfer speed and stability.

锁存信号也必须要与时钟信号协调才能显示出完整的图像。
The latched signal also needs to be coordinated with the clock signal to display the complete image.

这将模块上的通信引脚数量减少到两个：时钟信号和数据信号。
This reduces the number of communication pins on the module to just two: a clock signal and a data signal..

地址、数据输入和其它控制信号均于时钟信号相关。
Addresses, data inputs, and other control signals are all related to the clock signal.

PLL产生“时钟信号”,其振荡充当节拍器,为数字设备的和谐运行提供精确的时序参考。
PLLs generate‘clocking signals', whose oscillations act as a metronome that provides a precise timing reference for the harmonious operation of digital devices.

数据必须与时钟信号协调，以便传输到任何显示点。
The data must be coordinated with the clock signal in order to be transmitted to any display point.

另请注意，某些Ensembles同时需要时钟信号和MIDI输入才能产生声音。
Please also note some Ensembles require both a clock signal and MIDI input simultaneously to generate sound.