What is the translation of " 的时钟信号 " in English?

• clock signal
• clock signals

Examples of using 的时钟信号 in Chinese and their translations into English

DTE即数据终端设备，它通常使用DCE产生的时钟信号。
Model and usually uses the clock signals produced by DCE.

引脚19和20：引出I2C总线通信协议的时钟信号（SCL）和数据线（SDA）。
Pins 19 and 20: implement the clock signal(SCL) and data line(SDA) of the I2C bus communication protocol.

来自处理器的时钟信号是连续的，而EnDat协议规定，时钟只能在通信期间施加于编码器。
The clock signals from the processor are continuous, while the EnDat protocol specifies the clock must only be applied to the encoder during communication.

SPI是一种同步协议，这意味着它包含一个用于定时的时钟信号。
SPI is a synchronous protocol which means it includes a clock signal for timing.

新时代的作用是为系统提供基本的时钟信号。
The main function of this circuit card is to supply basic clock signals to the system.

SDA的数据的高或者低电平状态只有在SCL线的时钟信号是低电平时才能改变。
The high or low state of the data line, SDA, can change only when the clock signal on.

同时，进位端C0就输出一个进位脉冲，作为下一级计数的时钟信号。
At the same time, the carry terminal C0 outputs a carry pulse as a clock signal for the next stage count.

分频就是用同一个时钟信号通过一定的电路结构转变成不同频率的时钟信号。
Frequency division means that the same clock signal is used to convert clock signals of different frequencies through a certain circuit structure.

SDA的数据的高或者低电平状态只有在SCL线的时钟信号是低电平时才能改变。
Of the data line, SDA, can change only when the clock signal on SCL is low.

晶振的主要作用就是为了给系统提供基本的时钟信号。
The main function of this circuit card is to supply basic clock signals to the system.

时钟信号也可能由门控，即用一个控制信号使能或关闭电路某一部分的时钟信号。
A clock signal might also be gated, that is, combined with a controlling signal that enables or disables the clock signal for a certain part of a circuit.

晶体振荡器不会干扰机器的功能，它们可提供稳定可靠的时钟信号。
Crystal oscillators don't interfere with the function of the machine and they provide steady and reliable clock signals.

了解如何利用快而准确的抖动性能测量来验证您的时钟信号（使用R&S®FSWP相位噪声分析仪）.
Learn how to verify your clock signal by taking advantage of fast and precise jitter performance measurements(with R&S®FSWP phase noise analyzer).

通过提供DPWM模块可取得额外的分辨率，前提是该模块具有16个分别为250MHz的移相时钟信号。
This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz each.

SDA的数据的高或者低电平状态只有在SCL线的时钟信号是低电平时才能改变。
The high and low states of the data line can only change when the clock signal on the SCL line is LOW.

到一个数据网络的连接是由使用该设备产生的时钟信号的数据通信设备(DCE)，如调制解调器所组成。
The connection to a data network is made through data communication equipment(DCE) such as a modem, using the clocking signals generated by that device.

该值越小越容易生成稳定的时钟信号。
A smaller ESR indicates easier generation of stable clock signals.

这样可在PLL锁序列期间提供一个洁净的时钟信号。
Enables the provision of a clean clock signal during the PLL lock sequence.

由于没有使用一个单独的时钟信号，需要一个同步节点方法。
Since a separate clock signal is not used, a means of synchronizing the nodes is necessary.

该频率通常用于为系统内的数字集成电路提供稳定的时钟信号。
This frequency is commonly used to provide a stable clock signal for digital integrated circuits within a system.

在数字电路中，通常的时钟信号都是边沿变化快的信号，对外串扰大。
(5) In digital circuits, the usual clock signal is the edge changes fast signal, the external crosstalk is large.

在数字电路中，通常的时钟信号都是边沿变化快的信号，对外串扰大。
In digital circuits, the usual clock signals are signals with fast edge changes, and the external crosstalk is large.

在数字电路中，通常的时钟信号都是边沿变化快的信号，对外串扰大。
(5) In a digital circuit, the normal clock signal is a signal with a rapid edge change, and the external crosstalk is large.

例如，最近采用的子标准提供了一种可互操作的方法，用于同步分布在整个网络中的时钟信号。
For example, the recently adopted substandards provide an interoperable method of synchronizing the clock signals distributed throughout the network.

也就是说数据的传输没有时钟信号。
Data that is transmitted without an associated clock signal.

EM78P153K可由通过OSCI引脚输入的外部时钟信号驱动，如下图所示。
EM78156E can be driven by an external clock signal through the OSCI pin as shown in.

EM78P153K可由通过OSCI引脚输入的外部时钟信号驱动，如下图所示。
EM78P157N can be driven by an external clock signal through the OSCI pin as illustrated in the following figure.

定时器0溢出或ECI输入针脚上的外部时钟信号。
Timer 0 overflow, or an external clock signal on the ECI line.

其次，检测输出口的时钟锁存信号是否正常。
Detect the transmission of the clock lock signal is normal.

主机向每种卡的5号接点提供时钟信号，但各种卡的时钟频率可能不同。
A clock signal is provided by the host to contact no. 5 of each card but the clock rate may be different.