What is the translation of " VERILOG " in English?

• verilog

Examples of using Verilog in Chinese and their translations into English

什么是VerilogHDL？?
What is PLI of Verilog HDL?

VerilogHDL是一种硬件描述语言（HDL.
Verilog HDL is a Hardware Description Language(HDL).

熟练掌握Verilog或VHDL；.
Competency in Verilog or VHDL.

Verilog和VHDL就是这种硬件描述语言。
Verilog and VHDL are both hardware description languages.

最广泛使用的HDL语言是VHDL和VerilogHDL。
The most popular HDL languages are Verilog and VHDL.

Verilog和VHDL就是这种硬件描述语言。
Verilog and VHDL are known as Hardware Description Languages.

FPGA的编程语言有两种：VHDL和Verilog。
There are two major hardware description languages: VHDL and Verilog.

Verilog在工业界通用些，VHDL在大学较多。
My impression was more Verilog in academia, VHDL in industry.

这种语言以Verilog硬件描述语言为基础。
This implementation is translated to the Verilog hardware description language.

VHDL和VerilogHDL是世界上最流行的两种硬件描述语言，.
VHDL and Verilog HDL are the two most major Hardware Description Languages.

FPGA里面的模块和时序用VERILOGHDL编程实现。
The modules and timings in the FPGA are implemented using VERILOG HDL programming.

该编程语言基于Verilog，其通常用于编程计算机芯片。
The language is based on Verilog, which is commonly used to program computer chips.

IcarusVerilog是Verilog硬件描述语言的实现工具之一。
Icarus Verilog- Icarus Verilog is an implementation of the Verilog hardware description language.

该编程语言基于Verilog，其通常用于编程计算机芯片。
This language is based on Verilog, which is commonly used for developing computer chips program.

IcarusVerilog是Verilog硬件描述语言的实现工具之一。
Icarus Verilog is an implementation of the Verilog hardware description language.

使用Chisel描述的电路可以转换为Verilog，以进行综合和仿真。
Circuits described in Chisel can be converted to a description in Verilog for synthesis and simulation.

Verilog是由GatewayDesignAutomation公司于大约1984年开始发展。
Verilog was developed originally at Gateway Design Automation Corporation during the mid-eighties.

你可以从不同的硬件描述语言生成代码，包括：VHDL,SystemCandVerilog.
You can generate code in various Hardware Description Languages, including VHDL, SystemC and Verilog.

针对FPGA最常用的语言是Verilog和VHDL，两者均为硬件描述语言（HDL）。
The most popular languages for FPGAs have been Verilog and VHDL, both examples of hardware description languages(HDL).

随后，Verilog被提交到IEEE并成为IEEE1364-1995标准，通常称这一标准为Verilog-95。
Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.

数字ASIC的设计者通常使用硬件描述语言（HDL）（例如Verilog或VHDL）来描述ASIC的功能。
Designers of digital ASICs use a hardware description language(HDL), such as Verilog or VHDL, to describe the functionality of ASICs.

最初在VHDL或Verilog的RTL描述通过创造试验台刺激系统和观察结果模仿。
Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results.

Verilog及其姊妹语言VHDL是用于设计数字集成电路的两种代表性硬件定义语言(HDL)。
Verilog and its sister VHDL are examples of two HDLs(hardware definition languages) used to design digital integrated circuits.

软件编程的思想根深蒂固，看到Verilog或者VHDL就像看到C语言或者其它软件编程语言一样….
The idea of software programming is ingrained, and seeing Verilog or VHDL is like seeing a C language or other software programming language.

研究人员在一种叫作Verilog的程序语言中对基因-电路设计进行了具体化，Cello制作让它们起作用的DNA序列。
Researchers specify genetic-circuit designs in a programming language called Verilog, and Cello produces the DNA sequences that are required to make them work.

片上系统（SoC）片上网络（NoC）可重构计算现场可编程逻辑门阵列（FPGA）VHDLVerilogSystemVerilog硬件加速.
System-on-a-chip(SoC) Network-on-a-chip(NoC) Reconfigurable computing Field-programmable gate array(FPGA) VHDL Verilog SystemVerilog Hardware acceleration.

直到最近，FPGA的编程还需要硬件工程师能够用复杂、底层的硬件定义语言如Verilog进行编程和重新编程。
Until recently, programming FPGAs required hardware engineers, with programming and reprogramming carried out in complex, low-level hardware definition languages such as Verilog.

作为硬件行为级的建模语言，Verilog-AMS和VHDL-AMS分别是Verilog和VHDL的超集，而Verilog-A则是Verilog-AMS的一个子集。
As a hardware behavioral modeling language, Verilog-AMS and VHDL-AMS are supersets of Verilog and VHDL, respectively, while Verilog-A is a subset of Verilog-AMS.

根据以上设计方案，选用VerilogHDL进行设计，同时采用了Modelsim6.1b进行了仿真验证，最后在STratixIIEP2S180F1020I4芯片上进行了测试。
Based on the above design, selection of Verilog HDL design, while using Modelsim 6.1b to the simulation results, and finally STratix IIEP2S180F1020I4 chips were tested.

截止到0.9版，该工具提供了Verilog编译器（包含一个Verilog预处理器），并支持可插入后端（plug-inbackend），并通过一个虚拟机来对设计进行仿真。
As of release 0.9, Icarus is composed of a Verilog compiler(including a Verilog preprocessor) with support for plug-in backends, and a virtual machine that simulates the design.