Примери коришћења Conditional jump на Енглеском и њихови преводи на Српски
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Instead it keeps a shared history of all conditional jumps.
Assume, for example, that a conditional jump is taken every third time.
Hence, the big pattern history table must be shared among all conditional jumps.
Such a conditional jump can be predicted easily with a simple counter.
Two-way branching is usually implemented with a conditional jump instruction.
A conditional jump that controls a loop is best predicted with a special loop predictor.
Branch prediction attempts to guess whether a conditional jump will be taken or not.
A conditional jump in the bottom of a loop that repeats N times will be taken N-1 times and then not taken once.
A global branch predictor does not keep a separate history record for each conditional jump.
Only decrementation(combined with conditional jump) and incrementation exist(and halting).
A local branch predictor has a separate history buffer for each conditional jump instruction.
A conditional jump that goes many times one way and then the other way once is detected as having loop behavior.
A loop predictor is part of a hybrid predictor where a meta-predictor detects whether the conditional jump has loop behavior.
The first time a conditional jump instruction is encountered, there is not much information to base a prediction on.
The advantage of a shared history is that any correlation between different conditional jumps is part of making the predictions.
When it encounters a conditional jump that has been seen several times before then it can base the prediction on the history.
The branch predictor attempts to avoid this waste of time by trying to guess whether the conditional jump is most likely to be taken or not taken.
Conditional jumps that are taken every second time or have some other regularly recurring pattern are not predicted well by the saturating counter.
The advantage of the two-bit counter scheme over a one-bit scheme is that a conditional jump has to deviate twice from what it has done most in the past before the prediction changes.
The Intel Pentium MMX, Pentium II, and Pentium III have local branch predictors with a local 4-bit history anda local pattern history table with 16 entries for each conditional jump.
The history buffer is separate for each conditional jump instruction, while the pattern history table may be separate as well or it may be shared between all conditional jumps. .
For example, on early C compilers, while(1) was slower than for(;;) for an unconditional loop, because while(1) evaluated 1 andthen had a conditional jump which tested if it was true, while for(;;) had an unconditional jump. .
It is not known for certain whether a conditional jump will be taken ornot taken until the condition has been calculated and the conditional jump has passed the execution stage in the instruction pipeline(see fig. 1).
The early implementations of SPARC and MIPS(two of the first commercial RISC architectures) used single-direction static branch prediction:they always predict that a conditional jump will not be taken, so they always fetch the next sequential instruction.
Without branch prediction, the processor would have to wait until the conditional jump instruction has passed the execute stage before the next instruction can enter the fetch stage in the pipeline.
A conditional jump can either be"not taken" and continue execution with the first branch of code which follows immediately after the conditional jump, or it can be"taken" and jump to a different place in program memory where the second branch of code is stored.
The disadvantage is that the history is diluted by irrelevant information if the different conditional jumps are uncorrelated, and that the history buffer may not include any bits from the same branch if there are many other branches in between.
Following this, conditional jump instructions can be used to check the flags and branch to code that should run, e.g.: cmp eax, ebx jne do_something;… do_something:; do something here Flags are also used in the x86 architecture to turn on and off certain features or execution modes.
The latest processors also do the opposite when appropriate;they combine certain x86 sequences(such as a compare followed by a conditional jump) into a more complex micro-op which fits the execution model better and thus can be executed faster or with less machine resources involved.
They combine certain x86 sequences(such as a compare followed by a conditional jump) into a more complex micro-op which fits the execution model better and thus can be executed faster or with less machine resources involved.