英語 での Low-order の使用例とその 日本語 への翻訳
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Colloquial
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Ecclesiastic
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Computer
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Programming
The empty low-order bytes are cleared set to all'0.
When we take a measurement, we will simply discard the low-order 16 bits.
The low-order 16 bits of Xi are set to the arbitrary value 330E16.
Pure salvage claims are divided into“high-order” and“low-order” salvage.
In both high-order and low-order salvage the amount of the salvage award is based first upon the value of the property saved.
For NIFF mode, the following flags are defined for the low-order 24 bits.
Host software will then discard the low-order 16 bits and report the remainder directly as the voltage in millivolts RMS.
In this document,all references to"TOS" or the"TOS field" refer to the low-order 5 bits only.
In constructing the full sequence number, if the low-order 32 bits carried in the packet are lower in value than the low-order 32 bits of the receiver's sequence number counter, the receiver assumes that the high-order 32 bits have been incremented, moving to a new sequence number subspace.
In the unlikely event that b is greater than 2^64,then only the low-order 64 bits of b are used.
In constructing the full sequence number, if the low-order 32 bits carried in the packet are lower in value than the low-order 32 bits of the receiver's sequence number counter, the receiver assumes that the high-order 32 bits have been incremented, moving to a new sequence number subspace.
If the type long contains more than 32 bits,only the low-order 32 bits are used for these operations.
In section 4.2, made it clearer that options are identified by the full 8-bit Option Type,not by the low-order 5 bits of an Option Type.
The sender increments the sequence number(or ESN)counter for this SA and inserts the low-order 32 bits of the value into the Sequence Number field.
That is, a particular option is identified by a full 8-bit Option Type,not just the low-order 5 bits of an Option Type.
The sender increments the sequence number(or ESN)counter for this SA and inserts the low-order 32 bits of the value into the Sequence Number field.
In the unlikely event that b is greater than 2^64,then only the low-order 64 bits of b are used.
This is not in line with the general"right to left" design of the PDP-11,which would place the low-order 16 bits in the lower memory address.
(ii) The displayed efficiencies are only possible because very thin structures were considered,leading to low-order cavities(as described in reference 10 below).