英語 での Status register の使用例とその 日本語 への翻訳
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ISDIO Status Register.
Obtain output data of Status Register.
It is the'SEC' status register bit shown at the far left in Figure 1.
Get"WLAN" data of Status Register.
The STATUS register indicates the event that caused the interrupt.
HTTP transfer status register.
STAT: OPER: NTR Sets the negative transition of the OPERation status register.
Digi PC/8 Interrupt Status Register is at 0x140.
STAT: OPER Queries the event of the OPERation status register.
Is used to branch if some of the status register bits of the parallel port are set.
STAT: OPER: COND Queries the condition of the OPERation status register.
Is used to branch if some of the status register bits of the parallel port are cleared.
STAT: OPER: PTR Sets the positive transition of the OPERation status register.
The device will then set the Status register bit 5 high to indicate that the character memory is not available for writing.
STAT: OPER: ENAB Sets the enable register of the OPERation status register.
Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks.
Returns the wireless LAN application status register contents as a string.
In order to poll a status of an issued command,you need to read the Response Status Register.
In a Winbond NOR Flash memory device's datasheet, these status register bits are shown as BP0, BP1 and BP2.
The current status of the TCRIT1,TCRIT2 and TCRIT3 pins can be read back from the status registers.
At that time, just three Block Protection(BP)bits in the Flash IC's status register were enough to specify the portion of the total memory array that needed to be protected.
See the manual for the NE765 or compatible for details about the status register contents.
This may seem strange at first, but removing this dependency from a status register means that it is much easier to build a CPU which can issue multiple instructions every cycle.
When the measured temperature of a channel exceeds the respective threshold,a status bit is set in one of the status registers.
The FDC error status includes the three FDC status registers‘ST0',‘ST1', and‘ST2', as well as the location of the error(physical cylinder, head, and sector number, plus the"sector shift value", respectively).
The results are reported and continuously updated in the status registers STAT and OSTAT.
We explained how to read the status register in Tutorial 3, but in this tutorial we aren't going to use the entire status register- we're only going to explain how to get the processing status after issuing a command.
These events are summarized in the required structures, OPERation status register, and QUEStionable register. .