Examples of using Interrupt controller in English and their translations into Korean
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Colloquial
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Ecclesiastic
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Ecclesiastic
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Programming
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Computer
The Interrupt Controller.
Advanced Programmable Interrupt Controller.
The Interrupt Controller then activates the INT signal to the CPU.
Advanced Programmable Interrupt Controller.
The interrupt controller then sends an interrupt to the CPU.
Local Advanced Programmable Interrupt Controller.
The PCI And Peripheral Interrupt Controller(PPIC) 67 provides the ability to generate interrupts to both the local processor and the PCI bus.
Compare with Advanced Programmable Interrupt Controller(APIC).
A peripheral interrupt controller for routing a plurality of interrupt sources into a single interrupt input to said local processor;
Support in the Advanced Programmable Interrupt Controller(APIC).
Most x86 systems rely on either the i8259A Programmable Interrupt Controller(PIC) or a variant of the i82489 Advanced Programmable Interrupt Controller(APIC); today's computers include an APIC.
The cell processor 700 may also include an internal interrupt controller IIC.
The system board uses a programmable interrupt controller to monitor the priority of the requests from all devices.
The i960 Jx Microprocessor User's Manual provides full details on programming the local processor interrupt controller.
Some of them, like the 8224 clock generator, 8257 DMA controller, and 8259 interrupt controller, all of which are today integrated into the CPU, were mandatory for operation.
Because the x64 architecture is compatible with x86 operating systems, x64 systems must provide the same interrupt controllers as the x86.
Also connected to system bus 20 are memory controller 34,bus controller 36, and interrupt controller 38 which serve to aid in the control of data flow through system bus 20 between various peripherals, adapters, and devices.
Non-Intel based systems such as Alpha AXP basedPCs are free from these architectural constraints and so often use different interrupt controllers.
The APIC bus interface unit provides an interface to the three-wire Advanced Programmable Interrupt Controller(APIC) bus that allows I/O APIC emulation in software.
The vulnerability exists in the Advanced Programmable Interrupt Controller(APIC), which could allow an attack against the System Management Mode(SMM) memory area used by the operating system to interface with the boot environment like BIOS, EFI, or UEFI.
This issue affects virtual machines on which guest operating systems use Advanced Programmable Interrupt Controller(APIC) logical destination mode.
If implemented as part of the memory controller, interrupts are mapped into the system's memory address space.