Examples of using Local processor in English and their translations into Korean
{-}
-
Colloquial
-
Ecclesiastic
-
Ecclesiastic
-
Programming
-
Computer
It is programmable only through the local processor 34.
The local processor 34 has direct access to both PCI buses.
Fully programmable from the local processor.
The local processor operates out of its own 32-bit address space and not PCI address space.
The Local Bus Arbitration Unit controls the local processor backoff unit.
The local processor bus connects to P2P processor I/O pins to provide bus access to external devices.
Each channel has a PCI bus interface and a local processor local bus interface.
The local processor 42 cannot directly communicate with the network but, rather, it requests the Mate to communicate for it.
A value of"1" indicates communication with the local processor and a value of"2" indicates communication with the SSIB.
Each DMA channel uses direct addressing for both the PCI bus and the local processor local bus.
In this manner, both the type and the size of the local processor 42 can vary and still be accommodated by the Mate 10.
This 64-bit addressing extension is for outbound data transactions only(i.e. data transfers initiated by the local processor).
The XINT6, XINT7, and NMI interrupt inputs on the local processor receive inputs from multiple internal interrupt sources.
The address translation unit allows PCI transactions direct access to the local processor local memory 33.
The SSIB and the local processor are provided with the same ID for all the Mates in the system since only one communication path is provided therebetween.
The i960 Jx Microprocessor User's Manual provides full details on programming the local processor interrupt controller.
The nine interrupt pins of the local processor have the following definitions and programming options.
A peripheral interrupt controller for routing a plurality of interrupt sources into a single interrupt input to said local processor;
The i960 Jx Microprocessor User's Manual further describes the local processor interrupt and interrupt priority mechanisms.
Therefore, all of the local processors 42 interfaced with the various Mates 10 can utilize the SCM cable 16 to transmit baseband information to the LAN and carry on data communications apart from the video conferencing network.
Similarly, the server can be a centralized music information server which connects to the user's local processor via the internet.
In addition, the WAIT signal provides the local bus masters(except the local processor) to indicate additional wait states by wait state generator 109 are required during a memory access.
The PCI And Peripheral Interrupt Controller(PPIC) 67 provides the ability to generate interrupts to both the local processor and the PCI bus.
It can also receive EOI messages from the APIC bus and optionally interrupt the local processor to inform it that an EOI vector is available.
Since the APIC programming interface consists oftwo 32-bit memory locations, I/O APIC functionality can be emulated by the local processor in the P2P processor. .
Additionally, the user can dial"65" during a conference such that synthesized sounds from the local processor can be transmitted on the audio path.
Bus masters connected to the local bus consist of three DMA channels,primary PCI Address Translation Unit, secondary PCI Address Translation Unit, local processor, and external bus masters.
When a bus master requests the local bus, the Local Bus Arbitration Unit should first obtain control of the local bus from the local processor by asserting the HOLD request signal.
Housing 203 also holds a processor and local radio, such as a Bluetooth radio.
Generally, terminals have a monitor and a keyboard, but no processor or local disk drive.
