Examples of using Phy in English and their translations into Korean
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Colloquial
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Ecclesiastic
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Ecclesiastic
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Programming
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Computer
IT Estensione PHY.
PHY and protocol error triggers.
Integrated Ethernet MAC+ PHY.
Details about the PHY and MAC layers of DOCSIS 3.1.
Integrated Ethernet MAC+ PHY.
PHY channels contain a set of DI channels and UL channels.
GFD Kathrin Second Exam Medical Phy.
PHY channels contain a set of DI channels and UL channels.
Sub-carrier spacing and MAC/PHY enhancements.
Word Reactor: Word Reactor is a word game with phy.
The PHY channels comprise a set of DI channels and UL channels.
This was due to Alternative MAC/PHY(AMP).
The PHY channels may include a set of DI channels and UL channels.
If pull up SFP's TX_DISABLE pin, PHY IC be reset.
Various External PHY usable such as Switching PHY.
All-in-one Ethernet Controller: Hardware TCP/IP,MAC& PHY.
PHY 141 Foundations of Physics I OR PHY 151 Principles of Physics I.
In some embodiments, MAC and PHY processing may be integrated into a single circuit.
PHY 142 Foundations of Physics II OR PHY 152 Principles of Physics II.
The distance of the station-to-station directly from the LAN may be limited by the PHY performance.
The 1000BASE-T physical layer IC(PHY) can be accessed via I2C, allowing access to all PHY settings and features.
If no frame is receivedduring the selected slot, the processor can turn off the RF and PHY sections.
The additional coursework includes one semester of PHY 402 Senior Physics Lab and PHY 350 Science Curriculum Projects.
As such, reception of the payload may fail, but the 802.11 STA defers for the time indicated in PHY preamble.
Remote PHY, I-CMTS, and M-CMTS can all co-exist in the same chassis and use the same software base and configuration systems.
ULPI interface: for connecting high-speed USB peripheral(the STM32F407I integrates USB HS controller without any PHY device).
For instance, Faraday's customized Ethernet PHY can support high data transmission accuracy in 120-meter long cable, with an accuracy rate superior to the industry standard.
Faraday's complete IP set on 55nmLP SST embedded Flash process includes the standard cell libraries, memory compilers, diffusion programmable ROM, Via ROM, I/O cells, andlow power USB 2.0 OTG PHY.
Complementing the Host and Device Controllers is the robust,low power DesignWare SATA PHY, which includes unique built-in diagnostics allowing on-chip visibility into the link performance and ATE test vectors for at-speed production testing.
Using PVDF(polyvinylidene fluoride) for the func t iona l l a yer of the membrane and PET(polyester)non-woven fabric as the base layer allows the membrane to exhibit super ior phy s i cal s t rength and.