Примери коришћења Memory cells на Енглеском и њихови преводи на Српски
{-}
-
Colloquial
-
Ecclesiastic
-
Computer
-
Latin
-
Cyrillic
Start differentiating into effector and memory cells.
These memory cells immediately deploy the exact weapons needed.
Such systems operate on probability distribution vectors stored in memory cells and registers.
Induction of memory cells is the primary aim of vaccination.
This technology, which exploits the electrical property known as negative differential resistance andis called thin capacitively-coupled thyristor, is used to create memory cells capable of very high packing densities.
NAND flash memory cells can only be directly written to when they are empty.
The key difference between DDR andDDR2 is that for DDR2 the memory cells are clocked at 1 quarter(rather than half) the rate of the bus.
DRAM has memory cells paired with a transistor and capacitor requiring constant refreshing.
Most semiconductor memory is organized into memory cells or bistable flip-flops, each storing one bit(0 or 1).
These memory cells can be called upon to quickly eliminate a pathogen should subsequent infections occur.
Most semiconductor memory is organized into memory cells or bistable flip-flops, each and every storing 1 bit( or 1).
Memory cells generated by the HIV vaccine are activated when they learn HIV is present from the front-line troops.
This requires a 4-bit-deep prefetch queue,but, without changing the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.
DRAM contains memory cells that have a transistor and capacitor paired together, which is why they must be refreshed constantly.
Modern computers work on the basis of the simplest discrete logic- their elementary memory cells and computer modules can only perceive and process only zeros and units.
The number of CD8+ memory cells is shown to be controlled by a balance between IL-15 and IL-2.
In 2004, Krieger and Spitzer described dynamic doping of polymer and inorganic dielectric-like materials that improved the switching characteristics andretention required to create functioning nonvolatile memory cells.
The number of CD8+ memory cells is shown to be controlled by a balance between this cytokine and IL2.
The majority of one-off("soft") errors in DRAM chips occur as a result of background radiation, chiefly neutrons from cosmic ray secondaries,which may change the contents of one or more memory cells or interfere with the circuitry used to read/write them.
Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.
The 1-bit memory cells are grouped in small units called words which are accessed together as a single memory address.
Throughout the lifetime of an animal, these memory cells will"remember" each specific pathogen encountered, are able to mount a strong and rapid response if the same pathogen is detected again.
Original flash memory cells were often described as having one of two voltages stored in them, one for data 1 and another for data 0.
Sedgewick, Szymanski, and Yao provide a method that uses M memory cells and requires in the worst case only( λ+ μ)( 1+ c M- 1/ 2){\displaystyle(\lambda+\mu)(1+cM^{-1/2})} function evaluations, for some constant c, which they show to be optimal.
SSDs store data in flash memory cells that are grouped into pages, with the pages(typically 4 to 16 kB each) grouped together into blocks(typically 128 to 512 pages per block, e.g. totaling 512 kB per block in case of the 4/128 combination).
After the meeting in the mother's immune system generates"memory cells" that repeated contact(happening at the next pregnancy) produce antibodies(immunoglobulins), the G class, which cross the placenta and can lead to the development of hemolytic disease of the fetus and newborn.
SSDs store data in flash memory cells that are grouped into pages typically of 4 to 16 kB, grouped together into blocks of typically 128 to 512 pages.
Throughout the lifetime these memory cells will“remember” each specific pathogen encountered, and are able to mount a strong and rapid response if the pathogen(bad cell) is detected again.
As the feature size of flash memory cells reaches the minimum limit, further flash density increases will be driven by greater levels of MLC, possibly 3-D stacking of transistors, and improvements to the….