Examples of using Cray in English and their translations into Serbian
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Colloquial
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Ecclesiastic
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Computer
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Latin
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Cyrillic
Cray said to him.
I'm Janice Cray.
Cray, do you have her?
Owner of record. Cray.
Cray, why are you doing this?
That was Veronica Cray.
Cray and Nate were tight.
The German Bionic Cray+.
Cray, it's such a beautiful day.
John"… and Veronica Cray.
Cray, AMD to build 1.5 exaflops supercomputer for US government.
Harbinger, this is Senator Cray.
As much as I'd love a Cray Titan right now, it's not worth taking Henry's money.
I have a meeting with Scott Cray.
The mega-machine is officially called Cray XC50, but nicknamed ATERUI II.
I'm so glad to see you, Cray.
Seymour Cray, American computer scientist, founded the CRAY Computer Company d.
You should let me finish her, Cray.
Cray plans to make its AMD EPYC-based CS500 supercomputers available in summer 2018.
You haven't published in eight years, Cray.
In addition, Cray will offer 2U 2-way AMD EPYC-powered systems supporting up to 4 TB of memory.
Vector processing was especially popularized by Cray in the 1970s and 1980s.
The German Bionic Cray+ robot exoskeleton was specially developed for use in disaster areas.
Later, in the 1970s and1980s, SSDs were implemented in semiconductor memory for early supercomputers of IBM, Amdahl, and Cray,[16] but they were seldom used because of their prohibitively high price.
Cray this week announced plans to offer AMD's EPYC-based CS500 cluster supercomputers later this year.
Following the success of the CDC 6600 in 1964, the Cray 1 was delivered in 1976, and introduced internal parallelism via vector processing.
AMD and Cray have announced that they're building“Frontier,” a new supercomputer for the Department of Energy at Oak Ridge National Laboratory.
The technology incorporated in the Cray+ is based on the successful Cray X model, which was developed for implementation in industry and logistics where it has been used for some time.
The Cray CS500 clusters will be based on ultra-dense 2-way servers each featuring up to 64 cores, various storage options, and high-speed network connectivity.
The CDC 6600 designed by Seymour Cray in 1964 used a load/store architecture with only two addressing modes(register+register, and register+immediate constant) and 74 operation codes, with the basic clock cycle being 10 times faster than the memory access time.