Примеры использования Memory subsystem на Английском языке и их переводы на Русский язык
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Information disclosure vulnerability in kernel memory subsystem.
A memory subsystem is one of the key components of a microprocessors.
Elevation of privilege vulnerability in kernel memory subsystem.
The memory subsystem oracle combines cache line oracles and performs overall evaluation of the device behavior.
This utility measures throughput of cache& memory subsystem.
Huge state space of a memory subsystem makes its functional verification extremely labor consuming.
Elevation of privilege vulnerability in kernel shared memory subsystem.
Petrochenkov A Model-Based Approach to Design Test Oracles for Memory Subsystems of Multicore Microprocessors Proceedings of the Institute for System Programming.
QC-CR 1107034 EoP High Anonymous shared memory subsystem.
To be implemented efficiently, the method implies the following two restrictions on the memory subsystem under test:(1) requests to different cache lines are executed independently;(2) requests to the same cache line are serialized.
Memparam is a full parameter test of x86 CPU's memory subsystem!
Intel Optane SSD combined with Intel Memory Drive Technology adds SSD advantages to memory subsystem enabling transparent OS access to larger volume of hybrid memory, more extensive usage of large data sets and reduced overhead costs.
DRAM is, however,only one piece of the pie for achieving optimal memory subsystem performance.
One needs to estimate anddescribe the efficiency of interaction with the memory subsystem(features of the program's memory access profile), the efficiency of using a resource of parallelism built into the algorithm, the efficiency of using communication networks(features of the communication profile), the efficiency of input/output operations, etc.
It is reordered by the compiler, the processor and the memory subsystem to achieve maximum performance.
MaxBench is an OpenGL accelerated benchmarking program that will test thespeed of your CPU, video and memory subsystems.
A Model-Based Approach to Design Test Oracles for Memory Subsystems of Multicore Microprocessors.
It relieved many of the performance problems of the original Itanium processor,which were mostly caused by an inefficient memory subsystem.
The paper describes a method for constructing test oracles for memory subsystems of multicore microprocessors.
A reference model and the test oracle are divided into three levels:(1) the operation level,(2)the cache line level, and(3) the memory subsystem level.
Using the Intel Romley platform's available 24 DIMM(Dual Inline Memory Module)sockets connected to the Intel Xeon E5 family memory subsystem, we can gauge the sustained memory bandwidth in different memory configurations using SiSoft Sandra 2012 integrated STREAM memory benchmark with different memory channel population and memory clock speeds.
The tool consists of two parts:an architecture-independent test program generation core and MIPS64 memory subsystem specifications.
Case analysis showed up that the system's bottleneck is notthe processors' performance but the limitation of 32-bit architecture in a memory subsystem part that does not allow using efficiently more than 4 GB of the server's addressing space.
The analysis of the situation showed that the bottleneck of the system had nothing to do with processors' performance butit was the limitation of the 32-bit architecture regarding the memory subsystem that allowed using not more than 4 Gbytes of the server address space.
Combined with their support circuitry and amplifiers, the memory subsystem formed its own walk-in room.
Petrochenkov A Model-Based Approach to Design Test Oracles for Memory Subsystems of Multicore Microprocessors pp.
ADLAB discovered a possible memory overrun in the ISDN subsystem that may permit a local user to overwrite kernel memory by issuing ioctls with unterminated data.
A method of direct memory access subsystem verification used for"Elbrus" series microprocessors has been described.
It would require too much memory in the subsystem controller and impose excessive overhead.
Incorrect memory management in the filter subsystem could lead to denial of service.