Примеры использования Test generation на Английском языке и их переводы на Русский язык
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A Generic Knowledgebase for Test Generation.
Test Generation for Digital Hardware Based on High-Level Models.
To achieve this goal,a knowledgebase holding information relevant to test generation would be of a great help.
Automatic test generation for semantic analyzers of translators.
Smolov An Extended Finite State Machine-Based Approach to Code Coverage-Directed Test Generation for Hardware Designs pp.
Model-based test generation is widely spread in functional verification of hardware designs.
Unfortunately, no solution for the integration of various test generation methods into a unified environment is currently available.
Automated test generation is a promising direction in hardware verification research area.
This provides verification engineers with a flexible way to describe a wide range of test generation tasks with minimum effort.
Functional test generation methods based on models are widespread at the moment.
Automated methods of hardware verification are often based on models that are suitable for test generation and formal property checking.
In this paper, a new EFSM-based test generation approach is proposed and compared with the existing solutions.
The key issue of the state-of the-art verification approaches is to obtain a"good" model for automated test generation or formal property checking.
The article describes a control test generation method for discrete devices based on the genetic algorithm.
It is a flexible Ruby-based domain-specific language that allows describing a wide range of test generation tasks in terms of hardware abstractions.
In this paper, a functional test generation method based on model checking is proposed and compared to existing solutions.
The test generator has been developed using library version of the functional machine simulator that allowed to use the simulator as a reference model during the test generation.
The paper proposes a concept of a knowledgebase for test generation that can be used in a wide range of test generation tools.
An algorithm of test generation is proposed basing on test filtration generated for covering all transitions of the deterministic composition system.
It was always focused on testing effectiveness defined both by optimization of tests suites and by test generation algorithms including on-the-fly.
Nowadays a lot of various test generation tools are developed and applied to create tests for both software applications and hardware designs.
The first one is to give researchers a platform,where they could conduct preliminary experiments with different methods of test generation for digital circuits, in order to check different ideas.
Most the know methods for semantics test generation produce test suites by filtering a pre-generated set of random texts in the target language.
The toolkit allows analyzing HDL descriptions, reconstructing the underlying models(extended finite state machines, EFSMs) andusing the derived models for test generation, property checking and other tasks.
The paper presents an operating system configuration test generation method based on construction of covering arrays, that is ensuring coverage of all pairs, triple, etc.
Smolov An Extended Finite State Machine-Based Approach to Code Coverage-Directed Test Generation for Hardware Designs Proceedings of the Institute for System Programming.
If the hypothesis of links is true, an algorithm of test generation for a deterministic system is proposed basing on filtration of tests generated for covering all transitions of the composition.
Problem of uUndamped aAccelerometer in Headform Impact Test- Generation of Abnormal Acceleration in Headform Impact Tests- Causes and Solutions.
Our instruments are used for automatic test generation, tests porting, development of test suites, code coverage measurement, optimization, static analysis, automatic test run.
In spite of continuous development of computer-aided design(CAD)systems, test generation tools and approaches to analysis of circuits, verification remains the bottleneck of the microprocessor design cycle.