Examples of using Memory controller in English and their translations into Italian
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Colloquial
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Official
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Ecclesiastic
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Memory controller.
DRAM blocks, DBE and DFE are part of the memory controller(MC).
The memory controller now also supports DDR4-RAM, in this case up to 2400 MHz.
The 35W TDP rating includes the integrated GPU and memory controller.
The Llano memory controller has been greatly improved compared to the Stars cores.
HyperTransport technology, AMD64 technology, integrated memory controller.
The BIOS tries to configure the memory controller for normal operation.
Offers an integrated HD Graphics 4400 and a dual-channel DDR3 memory controller.
The CPU, as now known, has also a 4 channels memory controller, each with a bandwidth of 12.8GB/s.
Registered memory has a register between the DRAM modules and the memory controller.
IDS_SENSOR_NV_LOAD_MC"Shows GPU memory controller load percentage.".
GPU share access to the DDR3 memory type through a high-performance integrated memory controller.
The test in this case concerns the memory controller and memory latency.
Channel memory controller instead of 3
The BIOS tries to configure the memory controller Tested memory. .
Integrated memory controllerThe integrated memory controller is a key feature in Intel® QuickPath Architecture.
The BIOS will attempt to configure the memory controller for normal operation.
the test in this case concerns the memory controller and RAM.
pins is due to the quad channel memory controller and the high number of PCI Express lanes.
X memory controller seems to benefit less of the increased frequency
N455: Intel Atom CPU for Netbooks with integrated DDR3 memory controller and GMA 3150 GPU.
The System Agent is responsible for managing the memory controller, with reduced latencies compared to the memory controller of Clarkdale CPUs and comparable only to those of Lynnfield CPUs.
We focused only on testing the efficiency of the memory and then memory controller integrated into the CPU.
and all DRAMs are controlled by the processor's memory controller.
Second generation Maxwell also changed the ROP to memory controller ratio from 8:1 to 16:1.
by FinalWire, the test in this case concerns the memory controller and memory latency.
All CPUs will have a TDP of 130W, a quad-channel DDR3 memory controller with official support for 1600 MHz frequency.
also known as a Graphics and Memory Controller Hub(GMCH) in Intel systems.
In order to extend the memory's useable life, the SSD's memory controller employs various algorithms that spread the storage
hardware was crippled by a flaw in the CPU's memory controller, which prevented code execution out of system RAM.