Примеры использования Memory controller на Английском языке и их переводы на Русский язык
{-}
-
Official
-
Colloquial
The memory controller is integrated as a separate die.
It's main feature would be integrated single-channel memory controller.
Memory controllers are connected via internal bi-directional ring bus wrapped around the processor.
It is also Intel'sfirst integrated x86 processor, chipset and memory controller since 1994's 80386EX.
The memory controller is integrated into the CPU, the supported memory types depend on the CPU and socket used.
Fully buffered DIMM architecture introduces an advanced memory buffer(AMB) between the memory controller and the memory module.
It also uses a dual-channel LPDDR2 memory controller compared to Nvidia Tegra 2's single-channel memory controller. .
A 90-nanometer process GPU, a new ultra-threaded core processing architecture,a 128-bit ring-bus memory controller and up to 256 MB GDDR2 RAM.
The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. .
The library will consist of design elements from central processing units, memory controllers, peripherals, motherboards, and other components.
With this architecture, the memory controller does not write to the memory module directly; rather it is done via the AMB.
Unlike the parallel bus architecture of traditional DRAMs,an FB-DIMM has a serial interface between the memory controller and the AMB.
Socket 754, 939, andS1 processors have a memory controller integrated on the CPU die, replacing the traditional concept of FSB.
The device uses a 65 nm process, includes two to four cores, up to 24 MB on-die caches,Hyper-Threading technology and integrated memory controllers.
System-level design decisions such as whether ornot to include peripherals, such as memory controllers, can be considered part of the microarchitectural design process.
When a server is configured with Registered DIMMs, the memory bus functions in parallel mode, andall DRAMs are controlled by the processor's memory controller.
In order to extend the memory's useable life, the SSD's memory controller employs various algorithms that spread the storage of data across all memory cells.
The chipset consisted of six chips: a CPU and secondary cache controller, a buffer, a I/O cache andbus controller, a memory controller, and two data buffers.
Trinity will feature up to four x86-compatible cores, DDR3 memory controller and graphics controller of the Radeon HD 7000 with support for DirectX 11.
The memory controller, which handles communication between the CPU and RAM, was moved onto the processor die by AMD beginning with their AMD64 processors and by Intel with their Nehalem processors.
These are functionally equivalent to the previous generation,except they have a dual-channel DDR2 SDRAM memory controller which replaces the single-channel DDR SDRAM version.
With QuickPath, the processor has integrated memory controllers and interfaces the memory directly, using QPI interfaces to directly connect to other processors and I/O hubs.
This change in design was necessitated because, unlike the Athlon 64/Opteron,the Pentium 4 does not have an on-board memory controller thus requiring Nvidia to include one in the chipset like in older nForce2.
A memory controller is needed to managethe memory subsystem and different population rules governing the memory controller will affect the frequency/speed and latency at which a memory module can be addressed.
A-Series processors, manufactured on 32nm process technology, are equipped with DDR3 memory controller and integrated Radeon HD 6000 series graphics with support for DirectX 11 application programming interface.
The Radeon HD 3690, which was limited only to the Chinese market where it was named HD 3830, has the same core as the Radeon 3800 series butwith only a 128-bit memory controller and 256 MiB of GDDR3 memory. .
New features include: new RightMark Multi-Threaded Memory Test,support for AMD Athlon 64 X2 NPT DDR2 memory controller, support for Intel Core 2 processors, support for Extended Performance Profiles(EPP) SPD extension, new CPU Database entries, bugfixes.
The SCxxxx range of Geode devices are a single-chip version, comparable to the SiS 552, VIA CoreFusion or Intel's Tolapai,which integrate the CPU, memory controller, graphics and I/O devices into one package.
The memory controller runs at the same frequency as the CPU itself, and is able to run the system memory at 200 MHz(using PC-3200 memory sticks for 754 and 939, PC2-5300 for S1) or at lower speeds when using slower PC-1600, PC-2100 or PC-2700 RAM.
POWER10 processors will be manufactured using a 10 nm process and feature enhancements compared to its predecessor, POWER9, regarding core count,microarchitecture design, memory controllers, and I/O with support for OpenCAPI 4.0 and NVLink3.