What is the translation of " CLOCK CYCLE " in Chinese?

• 时钟周期
• 一个时钟周期

Examples of using Clock cycle in English and their translations into Chinese

Every clock cycle.
每一个时钟周期都.

The pins of Port 1 are sampled every clock cycle.
端口1的管脚每个时钟周期采.

Solely on clock cycle timing.
只基于时钟周期定时。

The pins of Port 1 are sampled every clock cycle.
端口1的引脚每个时钟周期都在采样。

Higher the clock cycle faster the processor is.
处理器的时钟周期越快。

Performed every clock cycle.
断每隔一个时钟周期。

During each SPI clock cycle, a full-duplex data transmission occurs.
在每个SPI时钟周期内，都会发生全双工数据传输。

Register each timer clock cycle.
断每隔一个时钟周期。

A clock cycle is a period of time in which a processor can carry out a given amount of instructions.
一个时钟周期就是一段时间，在这段时间内处理器能够执行给定数量的指令。

Once every clock cycle.
每一个时钟周期都.

They simply send more instructions in every clock cycle.
只是在每个时钟周期中发送了更多的指令。

It cannot be longer than one clock cycle, otherwise the first two flip-flop outputs will be set at the same time;
它不能超过一个时钟周期，否则前两个触发器输出将同时置1；.

You can read a C program and"see" every clock cycle.
你可以阅读一个C程序，“看到”每个时钟周期。

Without knowing the clock cycle times, it is impossible to state if one set of numbers is"faster" than another.
如果不知道时钟周期的时间，就不可能了解一组数字是否比另一组数字更快。

They simply send more instructions in every clock cycle.
他们只是在每个时钟周期中发送了更多的指令。

The Spectra 480 processes 4 pixels simultaneously in one clock cycle, while the average ISP can only process one pixel.
Spectra480在一个时钟周期同时处理4个像素，而一般的ISP只能处理1个。

Thus length of bus cycle in 8086 is four clock cycle.
的基本总线周期由4个时钟周期组成。

In other words, some people's physiological clock cycle may be more than 23 hours, and some people are close to 25 hours.
也就是说，有些人的生理时钟周期，可能是23小时多一点，有些人则接近25小时。

What this means is that two transfers occur every clock cycle.
但是，这意味着每个传输需要两个时钟周期。

Each AI core can implement 4096 MAC operations within one clock cycle, an exponential increase in comparison with the traditional CPU and GPU.
每个AICore可以在一个时钟周期内实现4096个MAC操作，这比传统的CPU和GPU提高了一个数量级。

This enables instructions to be executed in every clock cycle.
这个概念实现了将要执行的指令在每一个时钟周期。

This concept enables instructions to be executed in every clock cycle.
这个概念实现了每个时钟周期执行的指令。

Internal pipelined operation; column address can be changed every clock cycle.
内部数据流水线操作，列地址可在每个时钟周期里改变.

Assume it has a 15-stage pipeline and can issue four instructions every clock cycle.
假设该芯片有一个15步的工作流程，每个时钟周期可以发送4条指令。

Assume it has a 15-stage pipeline and can issue four instructions every clock cycle.
假设它有一个15-stage的pipeline，每个时钟周期可以发出四条指令。

For example, DDR3-2000 memory has a 1000 MHz clock frequency, which yields a 1 ns clock cycle.
举例来说，DDR3-2000内存的时钟频率是1000MHz，其时钟周期为1ns。

Our design allows the circuit to be rapidly morphed and reconfigured to perform a desired digital function in each clock cycle.
然而，他们的设计可以让电路可以迅速转变且重新配置，在每个时钟周期内完成特定的数字功能。

In this architecture, a single CPU overlaps fetching, decoding and executing instructions to process one instruction each clock cycle.
在这种架构中，一个CPU交替处理指令的读取、解码和执行，每个时钟周期处理一条指令。